The present invention relates to a method for manufacturing a semiconductor device and particularly to a method for forming the multilevel interconnection of a semiconductor device in which after a spacer made of an insulating material is formed on the side wall of the via hole, a second layer electrode is then formed.
Along with the miniaturization of LSI, several physical limitation problems appear in relation to the contacts. Among them are: broken conductive layers caused by the increase in geometric step, electromigration of the conductive material generated by miniaturization of the device and high resistance of the conductive layers, and stress migration.
The multilevel interconnection technique is suggested to solve the problems due to the miniaturization of the conductive layer in order to manufacture highly reliable and highly integrated semiconductor devices. This technique comprises the steps of forming an interlayer insulating layer by forming an insulating material on a semiconductor substrate on which a first layer electrode has been formed; forming a via hole by partially removing the interlayer insulating layer formed on the first layer electrode; and forming a second layer electrode by filling the via hole with conductive material.
Generally, in the multilevel interconnection technique, the second layer electrode is formed on the interlayer insulating layer which repeats the uneven surface formed by the first layer electrode, so that the topographical-like surface becomes larger than in the first layer electrode. Thus, since several problems are generated by the topographical-like surface, the uneven surface problem is overcome by carrying out the planarization process on the interlayer insulating layer first, and then forming the second layer electrode.
Referring to FIGS. 1A and 1B, the conventional method for planarizing an interlayer insulating layer and the conventional method for forming a second layer electrode by filling the via hole is illustrated.
The accompanying drawings are based on a semiconductor device where two transistors having one drain region 16 in common are formed on the semiconductor substrate 10 defined as an active region and a conductive material is then deposited on the source region 14 and the drain region 16 of the transistor to form a first layer electrode. At this time, the multilevel interconnection process is carried out to electrically connect the source region 14 of each transistor, the first layer electrodes 20 formed on the source region 14 of each transistor and the second layer electrode formed on the interlayer insulating layer.
First of all, a first dielectric layer 22 is formed on the semiconductor substrate 10 where the first layer electrodes 20 have been formed. Then, an insulating material such as a SOG (Spin-On-Glass) layer 24 is thickly formed on the whole surface of the first dielectric layer, is baked through a thermal process at a temperature of approximately 150.degree. C. to 450.degree. C. and is then etched back by anisotropic etching, thereby filling a re-entrant formed by the first layer electrode. At this time, the etching process is carried out until the surface of the first dielectric layer is exposed (refer to FIG. 1A). A second dielectric layer is formed in sequence on the whole surface of the semiconductor substrate where the re-entrant has been filled by the SOG layer, thereby completing the interlayer insulating layer. At this time, the interlayer insulating layer is constituted by the first dielectric layer, the SOG layer and the second dielectric layer, and is planarized by the second dielectric layer formed on the first dielectric layer where the reentrant is filled by the SOG layer. The via hole is then formed by partially removing the interlayer insulating layer laminated on the first layer electrode by a photolithography process and a conductive layer is formed by filling the via hole, depositing the conductive material on the whole surface of the semiconductor substrate, and patterning the deposited conductive material, thereby completing the second layer electrode 28.
In the method for forming the multilevel interconnection to form the second layer electrode after the planarization of the interlayer insulating film, the second layer electrode is formed on the planarized interlayer insulating layer by first planarizing the interlayer insulating layer by filling the re-entrant with the SOG layer and thus overcome the topographical effect due to the first layer electrode; thereby, overcoming the low reliability of the multilevel interconnection due to the uneven surface. However, since the etching ratio of the SOG layer to the dielectric layer is unequal in the planarization process, several problems are generated. Referring to FIGS. 2 and 3, the problems will be described.
FIG. 2 shows that the SOG layer is overetched due to the different etching ratios between the first dielectric layer and the SOG layer, when the SOG layer thickly coated on the first dielectric layer 22 is anisotropically etched. Generally, the SOG layer is thickly coated on the whole surface of the first dielectric layer, and is then baked through a thermal process at a temperature of approximately 150.degree. C. to 450.degree. C., while is to facilitate the following process by removing the water contained in the SOG layer through the baking process. At this time, the carbon content of the SOG layer is varied according to the temperature of the baking process and the etching ratio is varied according to the carbon content of the SOG layer. Generally, as the temperature is high, the carbon content of the SOG layer is small, and as the carbon content is small, the etching speed becomes faster than that of the first dielectric layer.
To make the etching rates of the SOG layer and the first dielectric layer equal, the baking process should be carried out by properly controlling the thermal processing temperature. But, since the conditions to be controlled are very difficult, as shown in FIG. 2, the re-entrant is not filled by the overetched SOG layer 24a and can remain. If the interlayer insulating layer is completed by forming the second dielectric layer when the re-entrant is not filled by the overetched SOG layer, the desirable planarization effect of the interlayer insulating layer by the SOG layer can not be obtained, so that problems are generated such as the electric opening of the conductive layer due to the voids of the conductive layer of the second layer electrode when the conductive material is deposited to form the second layer electrode on the interlayer insulating layer.
FIG. 3 shows that a thin SOG layer 24b is left on the first layer electrode where the via hole will be formed, since the SOG layer is underetched. In the conventional method for planarizing the interlayer insulating layer by filling the re-entrant, the material filled in the re-entrant is thickly coated on the whole surface of the first dielectric layer, and then etched-back until the upper surface of the first dielectric layer is exposed. This is to prevent hindering the formation of the highly reliable second layer electrode due to the several problems resulting from the non-etched and remaining materials on the first dielectric layer. The SOG layer used as the material for filling the re-entrant in the device shown in FIG. 2 has a property for strongly absorbing water. Accordingly, being exposed in air, the SOG layer absorbs the water contained in the air. As the SOG layer has the property of increasing volume by absorbing the water, it also decreases in volume under contrary conditions. In more detail as shown in FIG. 3, when the SOG layer is exposed in the air on the side wall of the via hole, the volume is expanded by the absorption of the water contained in the air, so that the adhesive between the first dielectric layer and second dielectric layer becomes weak and may destroy the laminated structure. When the second layer electrode is formed by depositing the conductive material on the via hole where the SOG layer has been exposed, the water contained in the SOG layer is moved to the conductive material constituted by the second layer electrode, thereby corroding the conductive layer and deteriorating the reliability of the semiconductor device.